Tuesday, June 18, 2013

One Hot Counter Structural VERILOG CODE and TEST FIXTURE

Counter One-Hot Verilog code:


`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module cont_one_hot_struct( start, I, RC, OC, S, V, clr, set, clk, cp);
input start, I, RC, S, V, clr, set, clk;
input [1:0] OC;
output [3:0]cp;
wire d0,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10;
wire q0,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10;
wire w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10;
wire Vcmp,RCcmp,Icmp,OC0,Scmp;

dff_syn_low_clr_set FF0 ( clk,d0,set,clr,q0,q_cmp0);
dff_syn_low_clr_set FF1 ( clk,d1,set,clr,q1,q_cmp1);
dff_syn_low_clr_set FF2 ( clk,d2,set,clr,q2,q_cmp2);
dff_syn_low_clr_set FF3 ( clk,d3,set,clr,q3,q_cmp3);
dff_syn_low_clr_set FF4 ( clk,d4,set,clr,q4,q_cmp4);
dff_syn_low_clr_set FF5 ( clk,d5,set,clr,q5,q_cmp5);
dff_syn_low_clr_set FF6 ( clk,d6,set,clr,q6,q_cmp6);
dff_syn_low_clr_set FF7 ( clk,d7,set,clr,q7,q_cmp7);
dff_syn_low_clr_set FF8 ( clk,d8,set,clr,q8,q_cmp8);
dff_syn_low_clr_set FF9 ( clk,d9,set,clr,q9,q_cmp9);
dff_syn_low_clr_set FF10 ( clk,d10,set,clr,q10,q_cmp10);

or O0(d0, start, q5, w0);
not N0(Vcmp, V);
and A0(w0, Vcmp, q10);

and A1(d1, I, q0);

or O2(d2, w2, q1);
not N1(RCcmp, RC);
and A2(w2, RCcmp, q3);

not N2(Icmp,I);
and A3(d3, Icmp, q0);

or O4(d4, w4, q2);
and A4(w4, RC, q3);

not N3(OC0, OC[0]);
and A5(d5, OC0, q4);

and A6(d6, q4, OC[0]);

or O7(d7, w7, w10);
and A7(w7, q4, OC[1]);
and A8(w10, V, q10);

and A9(d8, q6, Scmp);
not N4(Scmp,S);

or O9(d9, q7, w9);
and N5(w9, S, q6);

or O10(d10, q8, q9);

or CP0 (cp[0], q0,q3,q6,q7,q10);
or CP1 (cp[1], q2,q3,q5,q7,q8);
or CP2 (cp[2], q3,q5,q9,q10);
or CP3 (cp[3], q1,q6,q8);
endmodule


D flip flop code

dff_syn_low_clr_set


 `timescale 1ns / 1ps

//
//////////////////////////////////////////////////////////////////////////////////
module dff_syn_low_clr_set( clk,d,set,clr,q,q_cmp);
input clr, set, d, clk;
output q, q_cmp;
reg q;
always @(posedge (clk))
begin
if (clr==1'b0) begin q=1'b0; end
else if (set==1'b0) begin q=1'b1; end
else
begin
q=d;
end
end
assign q_cmp=~q;

endmodule










Verilog Test Fixture Code for One hot Counter


`timescale 1ns / 1ps
module cont_one_hot_struct_VTF;

                // Inputs
                reg start;
                reg I;
                reg RC;
                reg [1:0] OC;
                reg S;
                reg V;
                reg clr;
                reg set;
                reg clk;
                // Outputs
                wire [3:0] cp;
reg [10:0]yp,Y;
reg [3:0]cp_tc;
reg error;

parameter t0=11'b10000000000;
parameter t1=11'b01000000000;
parameter t2=11'b00100000000;
parameter t3=11'b00010000000;
parameter t4=11'b00001000000;
parameter t5=11'b00000100000;
parameter t6=11'b00000010000;
parameter t7=11'b00000001000;
parameter t8=11'b00000000100;
parameter t9=11'b00000000010;
parameter t10=11'b10000000001;
                cont_one_hot_struct uut ( .start(start),                .I(I),       .RC(RC), .OC(OC), .S(S),                 .V(V),    .clr(clr), .set(set),
                                .clk(clk), .cp(cp));
                initial begin
                                // Initialize Inputs
                                start = 0;
                                I = 0;
                                RC = 0;
                                OC = 0;
                                S = 0;
                                V = 0;
                                clr = 0;
                                set = 1;
                                clk = 0;
                                Y=11'b00000000000;

                                // Wait 100 ns for global reset to finish
                                #100;
                                start = 1;
                                clr=1;
      #10;
                                start = 0;
                                #100;
                                // Add stimulus here
                end
     
                                always
                                begin
                                #20 clk =~clk;
                                end
               

                               
                                always
                                begin
                                #200 I =~I;
                                end
                               
                                always
                                begin
                                #300 RC =~RC;
                                end
                               
                                always
                                begin
                                #400 OC =OC+1;
                                end
                               
                                always
                                begin
                                #600 S =~S;
                                end
                               
                                always
                                begin
                                #800 V =~V;
                                end
                               
                                always
                                begin
                                #2000  clr=~clr;
                                end
                               
                                always @(yp,I,S,RC,OC,V)
                                begin
                               
                                case (yp)
                                t0: if (I==1'b1) Y=t1;
                                                else Y=t3;
                                t1: Y=t2;
                                t3: if (RC==1'b1) Y=t4;
                                                else Y=t2;
                                t2: Y=t4;
                                t4: if(OC==2'b00) Y=t5;
                                else if(OC==2'b01) Y=t6;
                                else if(OC==2'b10) Y=t7;
                                t5: Y=t0;
                                t6: if(S==1'b1) Y=t9;
                                                else Y=t8;
                               
                                t7: Y=t9;
                                t8: Y=t10;
                                t9: Y=t10;
                                t10: if(V==1'b1) Y=t7;
                                                else Y=t0;
                                               
                                default: Y=0;
                                endcase
                               
                                end
                               
                               
                                always@(posedge clk)
                                begin
                                                if(clr==1'b0) yp=11'b00000000000;
                                else if (start==1'b1) yp=t0;
                                else yp=Y;
                               
                                end
always @(yp)
                                begin
                                case(yp)
                               
                                t0 : cp_tc=4'b0001;
                                t1 : cp_tc=4'b1000;
                                t2 : cp_tc=4'b0010;
                                t3 : cp_tc=4'b0111;
                                t4 : cp_tc=4'b0000;
                                t5 : cp_tc=4'b0110;
                                t6 : cp_tc=4'b1001;
                                t7 : cp_tc=4'b0011;
                                t8 : cp_tc=4'b1010;
                                t9 : cp_tc=4'b0100;
                                t10 : cp_tc=4'b0101;
                                default: cp_tc =4'b0000;
                                endcase                              
                                end
                               
                                always
                                begin
                                #1 if (cp==cp_tc) error=0;
                                else error=1;
                                end
                               
endmodule

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