Bit slicing is a method of combining processor modules to multiply the word length. In a bit-sliced processor, each module contains an ALU (arithmetic-logic unit) usually capable of handling a 4-bit field. By combining two or more identical modules, it is possible to build a processor that can handle any multiple of this value, such as 8 bits, 12 bits, 16 bits, 20 bits, and so on. Each module is called a slice. The control lines for all the slices are connected effectively in parallel to share the processing "work" equally.
VERILOG CODE:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module ALUbitSlice(a,b,cin,out,cout,control );
input a,b,cin;
input [2:0]control;
output out,cout;
reg out, cout;
always @(control)
begin
case
(control)
0:
begin
out
= a^b^cin;
cout
= (b&&cin)||(a&&cin)||(a&&b);
end
1:
begin
out
= a^(~b)^cin;
cout
= ((~b)&&cin)||(a&&cin)||(a&&(~b));
end
2:
begin out = a&b;
cout
= 0;
end
3:
begin
out
= a&(~b);
cout
=0;
end
4:
begin
out = a||b;
cout
=0;
end
5:
begin
out
= a||(~b);
cout
=0;
end
6:
begin
out
= b;
cout
=0;
end
7: begin
out
= a;
cout
=0;
end
default:
out=0;
endcase
end
endmodule
Verilog Test Fixture
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
module ALUbitSliceVTF;
reg
[5:0] ctr;
reg
out_tc;
reg
cout_tc;
reg
error;
reg
clk;
wire
out;
wire
cout;
//
Instantiate the Unit Under Test (UUT)
ALUbitSlice
uut (
.a(ctr[5]),
.b(ctr[4]),
.cin(ctr[3]),
.out(out),
.cout(cout),
.control(ctr[2:0])
);
initial
begin
//
Initialize Inputs
ctr
= 0;
clk
=0;
error
=0;
//
Wait 100 ns for global reset to finish
#100;
end
always begin
#10 clk= ~clk;
end
always @ (posedge clk)
begin
ctr = ctr +1;
end
always
begin
case
(ctr[2:0])
0:
begin
out_tc
= ctr[5]^ctr[4]^ctr[3];
cout_tc
= (ctr[4]&&ctr[3])||(ctr[5]&&ctr[3])||(ctr[5]&&ctr[4]);
end
1:
begin
out_tc
= ctr[5]^(~ctr[4])^ctr[3];
cout_tc
=
((~ctr[4])&&ctr[3])||(ctr[5]&&ctr[3])||(ctr[5]&&(~ctr[4]));
end
2:
begin out_tc = ctr[5]&ctr[4];
cout_tc
= 0;
end
3:
begin
out_tc
= ctr[5]&(~ctr[4]);
cout_tc
=0;
end
4:
begin
out_tc = ctr[5]||ctr[4];
cout_tc
=0;
end
5:
begin
out_tc
= ctr[5]||(~ctr[4]);
cout_tc
=0;
end
6:
begin
out_tc
= ctr[4];
cout_tc
=0;
end
7: begin
out_tc
= ctr[5];
cout_tc
=0;
end
default:
out_tc=0;
endcase
#1 if
(out== out_tc && cout==cout_tc) error=0;
else
error=1;
end
endmodule