Sunday, December 11, 2016

Verilog D flip flop with synchronous set and clear





DFF code


`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module DFFsynlowclrset( clk,d,set,clr,q,q_cmp  );
input clk,d,set,clr ;
output q,q_cmp ;
reg q;
reg q_cmp;
always @ (posedge (clk))
begin
if (clr==1'b0) begin q=1'b0; q_cmp=1'b1; end
else if (set==1'b0) begin q=1'b1; q_cmp=1'b0; end
else
begin
case (d)
                1'b0: begin q=1'b0; q_cmp=1'b1; end
                1'b1: begin q=1'b1; q_cmp=1'b0; end
                                default begin q=1'bZ; q_cmp=1'bZ; end
endcase
end
end
endmodule
`timescale 1ns / 1ps


Test Code


////////////////////////////////////////////////////////////////////////////////
module DFFsynlowclrsetVTF;
                reg clk, d,set,clr;
                wire q, q_cmp;
                reg qtc, q_cmptc, error;
                DFFsynlowclrset uut (
                                .clk(clk),
                                .d(d),
                                .set(set),
                                .clr(clr),
                                .q(q),
                                .q_cmp(q_cmp)
                );
                initial begin
                                clk = 0;
                                d = 0;
                                set = 1;
                                clr = 1;
                                #100;
                end
                                initial
                                begin
                                $monitor($time, "clk=%b clr=%b set=%b d=%b q=%b q_cmp=%b qtc=%b q_cmp=%b error=%b",
                                clk,clr,set,d,q,q_cmp,qtc,q_cmptc,error);
                                end
                                always begin
                                #10 clk=~clk;
                                end                       
                                always
                                begin: testloop
                                integer c;
                                for (c=0 ; c<64; c=c+1)
                                begin: c_loop
                                #20 clr <= ~((~c[5]&~c[4]&~c[3]&~c[2]&~c[1]&~c[0])|(c[5]&c[4]&~c[3]&~c[2]&c[1]&c[0])
                                                                                                |(~c[5]&~c[4]&~c[3]&c[2]&~c[1]&c[0]));
                                                set <=~((~c[5]&~c[4]&~c[3]&c[2]&~c[1]&c[0])|(~c[5]&~c[4]&c[3]&~c[2]&~c[1]&~c[0])
                                                |(c[5]&~c[4]&~c[3]&~c[2]&~c[1]&c[0])|(~c[5]&~c[4]&~c[3]&c[2]&c[1]&~c[0]));
                                                d <= c[3];
                                                end
                                                #250 error=1;
                                                end
                                                always @ (posedge (clk))
begin
if (clr==1'b0) begin qtc=1'b0; q_cmptc=1'b1; end
else if (set==1'b0) begin qtc=1'b1; q_cmptc=1'b0; end
else
begin
case (d)
                1'b0: begin qtc=1'b0; q_cmptc=1'b1; end
                1'b1: begin qtc=1'b1; q_cmptc=1'b0; end
                default begin qtc=1'bZ; q_cmptc=1'bZ; end
endcase
#1 if ((q==qtc)&&(q_cmp==q_cmptc)) error =0;
else error=1;
end
end

endmodule
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