Verilog 3x8 decoder with enable (Behavioral)
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module dec3x8enbehav(i,en,dec);
input [2:0]i;
input en;
output [7:0]dec;
reg [7:0]dec;
always @ (i or en)
begin
if (en==0) dec=7'b00000000;
else
if (en==1)
case
(i)
0
: dec=7'b00000001;
1
: dec=7'b00000010;
2
: dec=7'b00000100;
3
: dec=7'b00001000;
4
: dec=7'b00010000;
5
: dec=7'b00100000;
6
: dec=7'b01000000;
7
: dec=128;
default:dec=256;
endcase
else
dec=256;
end
endmodule
Test
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
module dec3x8enbehavVtf;
reg [2:0] i;
reg [2:0] ctr;
reg en;
wire [7:0] dec;
reg [7:0] dtc;
reg error;
reg clk;
dec3x8enbehav uut
( .i(ctr), .en(en), .dec(dec) );
initial begin
i
= 0;
clk=0;
ctr=0;
en=0;
#100;
end
always
begin
#20 clk = ~clk;
end
always
begin
#300 en = ~en;
end
always @
(posedge(clk))
begin
ctr = ctr+1;
end
always @ (ctr or
en)
begin
if (en==0)
dtc=7'b00000000;
else
if (en==1)
case(ctr)
0
: dtc=8'b00000001;
1
: dtc=8'b00000010;
2
: dtc=8'b00000100;
3
: dtc=8'b00001000;
4
: dtc=8'b00010000;
5
: dtc=8'b00100000;
6
: dtc=8'b01000000;
7
: dtc=8'b10000000;
default:dtc=8'b11111111;
endcase
end
always @(dec,dtc)
begin
if (dec==(dtc))
error = 0;
else
error = 1;
end
endmodule
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