3x8 Decoder Structural Verilog Code and Test Fixture

This is the 3 to 8 decoder verilog code (.v)

`timescale 1ns / 1ps
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module dec3x8struct( bi,d);
input[2:0]bi;

output[7:0]d;
wire w;
dec2x4en_case dec0 (bi[1:0],bi[2],d[7:4]);
dec2x4en_case dec1 (bi[1:0],w,d[3:0]);
not(w,bi[2]);


endmodule

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`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

module dec2x4en_case(i,en,dec);

input [1:0]i;

input en;

output [3:0]dec;

reg [3:0]dec;

always @ (i or en)

begin

if (en==0) dec=4'b0000;

else if (en==1)

case (i)

0 : dec=4'b0001;

1 : dec=4'b0010;

2 : dec=4'b0100;

3 : dec=4'b1000;

default:dec=4'b1111;

endcase

else dec=4'b1111;

end

endmodule

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Verilog Test Fixture for 3x8 decoder:

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////

module dec3x8structVTF;

reg [2:0] bi;

reg [2:0] ctr;

wire [7:0] d;

reg [7:0] dtc;

reg error;

reg clk;

// Instantiate the Unit Under Test (UUT)

dec3x8struct uut (.bi(ctr), .d(d));

initial begin

// Initialize Inputs

bi = 0;

clk=0;

ctr=0;

// Wait 100 ns for global reset to finish

#100;

   end

always

begin

#20 clk = ~clk;

end

   

always @ (posedge(clk))

begin

ctr=ctr+1;

end

always @(ctr)

begin

case(ctr)

0 : dtc=8'b00000001;

1 : dtc=8'b00000010;

2 : dtc=8'b00000100;

3 : dtc=8'b00001000;

4 : dtc=8'b00010000;

5 : dtc=8'b00100000;

6 : dtc=8'b01000001;

7 : dtc=8'b10000000;

default:dtc=8'b11111111;

endcase

end

always @(d,dtc)

begin

if (d==dtc) error = 0;

else error = 1;

end

endmodule