N bit Programmable Counter Verilog Code and Test Fixture Test Code

This is the Verilog Code for N bit Counter or Programmable Counter:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//
module progct_nbit( pcc,clr,in,out,clk);

parameter n=4;
parameter m=2;//increment value, when pcc=4

input [1:0]pcc;
input [n-1:0] in;
input clr;
input clk;
output [n-1:0] out;
reg [n-1:0] out;

integer i;

initial begin
out=0;
end

always @ (posedge clk)
begin

if(clr==0)
begin
for(i=0; i<n; i=i+1)
begin
out[i]=1'b0;
end
end

else
begin
case(pcc)
0: out=out;
1: out=in;
2: out=out+1;
3: out=out+m;
default:out=out;
endcase
end
end
endmodule

---

Verilog Test Fixture:

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////

module progctr_nbitVTF;

// Inputs
reg [1:0] pcc;
reg clr;
reg [3:0] in;
reg clk;
reg error;
reg [3:0]out_tc;

// Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)
progct_nbit uut (
.pcc(pcc),
.clr(clr),
.in(in),
.out(out),
.clk(clk)
);

initial begin
// Initialize Inputs
pcc = 0;
clr = 1;
in = 4;
clk = 0;
out_tc=0;
error=0;

// Wait 100 ns for global reset to finish
#100;
   
end
     
always
begin
#10 clk=~clk;
end
always
begin
#70 pcc=pcc+1;
end

always
begin
#270 clr=~clr;
end

always @(posedge clk)
begin
if(clr==0)
begin
out_tc=0;
end
else
begin
if(pcc==0) begin out_tc=out_tc; end
else if(pcc==1) begin out_tc=in; end
else if(pcc==2) begin out_tc=out_tc+1; end
else if(pcc==3) begin out_tc=out_tc+2; end
end
#1 if(out==out_tc) error=0;
else error=1;
end

endmodule