N- bit arithmetic shifter Verilog Code:
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module nBitArithShifterGen(in, out, control);
parameter n=4;
input [n-1:0]
in;
output [n-1:0]
out;
reg [n-1:0]
out;
input [2:0]control;
integer i;
always @ (control or in)
begin
case
(control)
0:
out = in*2;
1:
out = in*4;
2:
out = in;
3:
out = in/2;
4:
out = in/4;
5:
out = 0;
6:
begin
for(i=0;
i<n; i=i+1)
begin
out[i]=1'b1;
end
end
7: begin
for(i=0;
i<n; i=i+1)
begin
out[i]=1'bZ;
end
end
default:
out=0;
endcase
end
endmodule
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
module shifterVTF;
//
Inputs
reg
[3:0] in;
reg
[2:0]ctr;
reg
error;
reg
clk;
reg
[3:0]out_tc;
//
Outputs
wire
[3:0] out;
//
Instantiate the Unit Under Test (UUT)
nBitArithShifterGen
uut (
.in(in),
.out(out),
.control(ctr)
);
initial
begin
//
Initialize Inputs
in
= 2;
ctr
= 0;
error
=0;
clk=0;
//
Wait 100 ns for global reset to finish
#100;
end
always
begin
#20 clk=~clk;
end
always @ (posedge(clk))
begin
ctr=ctr+1;
end
always @(ctr or in)
begin
case (ctr)
0:
out_tc = in*2;
1:
out_tc = in*4;
2:
out_tc = in;
3:
out_tc = in/2;
4:
out_tc = in/4;
5:
out_tc = 0;
6: out_tc = 4'b1111;
7:
out_tc = 4'bZZZZ;
default:
out_tc=0;
endcase
end
always
@(out,out_tc)
begin
if(out==out_tc)
error=0;
else
error=1;
end
endmodule
