Verilog 4x16 decoder using 3x8 decoder module
code for 4x16 decoder
`timescale
1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module
dec4x16struct( bi,d);
input[3:0]bi;
output[15:0]d;
dec3x8enbehav
dec0 (bi[2:0],bi[3],d[15:8]);
dec3x8enbehav
dec1 (bi[2:0],~bi[3],d[7:0]);
endmodule
code for 3x8 decoder
`timescale
1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module
dec3x8enbehav(i,en,dec);
input
[2:0]i;
input en;
output
[7:0]dec;
reg
[7:0]dec;
always @ (i
or en)
begin
if (en==0)
dec=7'b00000000;
else if (en==1)
case
(i)
0
: dec=7'b00000001;
1
: dec=7'b00000010;
2
: dec=7'b00000100;
3
: dec=7'b00001000;
4
: dec=7'b00010000;
5
: dec=7'b00100000;
6
: dec=7'b01000000;
7
: dec=128;
default:dec=256;
endcase
else dec=256;
end
endmodule
Test Code
`timescale
1ns / 1ps
module
dec4x16structVTF;
reg [3:0] bi; reg [3:0] ctr;
wire [15:0] dec;
reg [15:0] dtc;
reg error, clk;
dec4x16struct uut ( .bi(ctr), .d(dec) );
initial begin
bi = 0;
clk=0;
ctr=0;
#100;
end
always
begin
#20 clk = ~clk;
end
always @ (posedge(clk))
begin
ctr = ctr+1;
end
always @ (ctr)
begin
case(ctr)
0 : dtc=1;
1 : dtc=2;
2 : dtc=4;
3 : dtc=8;
4 : dtc=16;
5 : dtc=32;
6 : dtc=64;
7 : dtc=128;
8 : dtc=256;
9 : dtc=512;
10 : dtc=1024;
11 : dtc=2048;
12 : dtc=4096;
13 : dtc=8192;
14 : dtc=16384;
15 : dtc=32768;
default:dtc=65535;
endcase
end
always @(dec,dtc)
begin
if (dec==(dtc)) error = 0;
else error = 1;
end
endmodule
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