Verilog 2 to 1 mux gate ( 2 to 1 multiplexer )

2 to 1 multiplexer code

mux2by1gate.v

`timescale 1ns / 1ps

module mux2by1gate( I0, I1, S, Z );

                input I0, I1, S ;

                output Z;

                wire w0, w1 ;

                and a0 (w0,I0, ~S);

                and a1 (w1, I1, S);

                or o1 (Z, w0, w1);

endmodule

Test Code

testf.v

`timescale 1ns / 1ps

module test;

// Inputs

                reg[2:0] count;

// Outputs

                reg Z_tc, error ;

                wire Z;

                mux2by1gate uut (.I0(count[1]), .I1(count[0]), .S(count[2]), .Z(Z));

                initial begin

                                count = 0;

                                Z_tc = 0;

                                #100;

                end

                always

                begin

                #20 count = count+1;

                if (count[2:0]==3'b000) begin Z_tc=1'b0; end

                else if (count[2:0]==3'b001) begin Z_tc=1'b0; end

                else if (count[2:0]==3'b010) begin Z_tc=1'b1; end

                else if (count[2:0]==3'b011) begin Z_tc=1'b1; end

                else if (count[2:0]==3'b100) begin Z_tc=1'b0; end

                else if (count[2:0]==3'b101) begin Z_tc=1'b1; end

                else if (count[2:0]==3'b110) begin Z_tc=1'b0; end

                else if (count[2:0]==3'b111) begin Z_tc=1'b1; end

                end

                always

                begin

                #1 if (Z==Z_tc) error =0;

                else error=1;

                end

endmodule