Sunday, December 11, 2016

Verilog D flip flop with synchronous set and clear





DFF code


`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module DFFsynlowclrset( clk,d,set,clr,q,q_cmp  );
input clk,d,set,clr ;
output q,q_cmp ;
reg q;
reg q_cmp;
always @ (posedge (clk))
begin
if (clr==1'b0) begin q=1'b0; q_cmp=1'b1; end
else if (set==1'b0) begin q=1'b1; q_cmp=1'b0; end
else
begin
case (d)
                1'b0: begin q=1'b0; q_cmp=1'b1; end
                1'b1: begin q=1'b1; q_cmp=1'b0; end
                                default begin q=1'bZ; q_cmp=1'bZ; end
endcase
end
end
endmodule
`timescale 1ns / 1ps


Test Code


////////////////////////////////////////////////////////////////////////////////
module DFFsynlowclrsetVTF;
                reg clk, d,set,clr;
                wire q, q_cmp;
                reg qtc, q_cmptc, error;
                DFFsynlowclrset uut (
                                .clk(clk),
                                .d(d),
                                .set(set),
                                .clr(clr),
                                .q(q),
                                .q_cmp(q_cmp)
                );
                initial begin
                                clk = 0;
                                d = 0;
                                set = 1;
                                clr = 1;
                                #100;
                end
                                initial
                                begin
                                $monitor($time, "clk=%b clr=%b set=%b d=%b q=%b q_cmp=%b qtc=%b q_cmp=%b error=%b",
                                clk,clr,set,d,q,q_cmp,qtc,q_cmptc,error);
                                end
                                always begin
                                #10 clk=~clk;
                                end                       
                                always
                                begin: testloop
                                integer c;
                                for (c=0 ; c<64; c=c+1)
                                begin: c_loop
                                #20 clr <= ~((~c[5]&~c[4]&~c[3]&~c[2]&~c[1]&~c[0])|(c[5]&c[4]&~c[3]&~c[2]&c[1]&c[0])
                                                                                                |(~c[5]&~c[4]&~c[3]&c[2]&~c[1]&c[0]));
                                                set <=~((~c[5]&~c[4]&~c[3]&c[2]&~c[1]&c[0])|(~c[5]&~c[4]&c[3]&~c[2]&~c[1]&~c[0])
                                                |(c[5]&~c[4]&~c[3]&~c[2]&~c[1]&c[0])|(~c[5]&~c[4]&~c[3]&c[2]&c[1]&~c[0]));
                                                d <= c[3];
                                                end
                                                #250 error=1;
                                                end
                                                always @ (posedge (clk))
begin
if (clr==1'b0) begin qtc=1'b0; q_cmptc=1'b1; end
else if (set==1'b0) begin qtc=1'b1; q_cmptc=1'b0; end
else
begin
case (d)
                1'b0: begin qtc=1'b0; q_cmptc=1'b1; end
                1'b1: begin qtc=1'b1; q_cmptc=1'b0; end
                default begin qtc=1'bZ; q_cmptc=1'bZ; end
endcase
#1 if ((q==qtc)&&(q_cmp==q_cmptc)) error =0;
else error=1;
end
end

endmodule

Verilog 2 to 1 mux gate ( 2 to 1 multiplexer )






2 to 1 multiplexer code

mux2by1gate.v
`timescale 1ns / 1ps
module mux2by1gate( I0, I1, S, Z );
                input I0, I1, S ;
                output Z;
                wire w0, w1 ;
                and a0 (w0,I0, ~S);
                and a1 (w1, I1, S);
                or o1 (Z, w0, w1);
endmodule






Test Code

testf.v
`timescale 1ns / 1ps
module test;
// Inputs
                reg[2:0] count;
// Outputs
                reg Z_tc, error ;
                wire Z;
                mux2by1gate uut (.I0(count[1]), .I1(count[0]), .S(count[2]), .Z(Z));
                initial begin
                                count = 0;
                                Z_tc = 0;
                                #100;
                end
                always
                begin
                #20 count = count+1;
                if (count[2:0]==3'b000) begin Z_tc=1'b0; end
                else if (count[2:0]==3'b001) begin Z_tc=1'b0; end
                else if (count[2:0]==3'b010) begin Z_tc=1'b1; end
                else if (count[2:0]==3'b011) begin Z_tc=1'b1; end
                else if (count[2:0]==3'b100) begin Z_tc=1'b0; end
                else if (count[2:0]==3'b101) begin Z_tc=1'b1; end
                else if (count[2:0]==3'b110) begin Z_tc=1'b0; end
                else if (count[2:0]==3'b111) begin Z_tc=1'b1; end
                end
                always
                begin
                #1 if (Z==Z_tc) error =0;
                else error=1;
                end

endmodule

Verilog 4x16 decoder (structural)

Verilog 4x16 decoder using 3x8 decoder module


code for 4x16 decoder

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////

module dec4x16struct( bi,d);
input[3:0]bi;
output[15:0]d;
dec3x8enbehav dec0 (bi[2:0],bi[3],d[15:8]);
dec3x8enbehav dec1 (bi[2:0],~bi[3],d[7:0]);
endmodule



code for 3x8 decoder


`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module dec3x8enbehav(i,en,dec);
input [2:0]i;
input en;
output [7:0]dec;
reg [7:0]dec;
always @ (i or en)
begin
if (en==0) dec=7'b00000000;
                                else if (en==1)
                                                case (i)
                                                                0 : dec=7'b00000001;
                                                                1 : dec=7'b00000010;
                                                                2 : dec=7'b00000100;
                                                                3 : dec=7'b00001000;
                                                                4 : dec=7'b00010000;
                                                                5 : dec=7'b00100000;
                                                                6 : dec=7'b01000000;
                                                                7 : dec=128;
                                                                default:dec=256;
                                                endcase
                                else dec=256;
end
endmodule


Test Code


`timescale 1ns / 1ps
module dec4x16structVTF;
                reg [3:0] bi; reg [3:0] ctr;
                wire [15:0] dec;
                reg [15:0] dtc;
                reg error, clk;
                dec4x16struct uut (         .bi(ctr), .d(dec) );
                initial begin
                                bi = 0;
                                clk=0;
                                ctr=0;
                                #100;
   end
                always
                begin
                #20 clk = ~clk;
                end
                always @ (posedge(clk))
                begin
                ctr = ctr+1;
                end
                always @ (ctr)
                begin
                case(ctr)
                                0 : dtc=1;
                                1 : dtc=2;
                                2 : dtc=4;
                                3 : dtc=8;
                                4 : dtc=16;
                                5 : dtc=32;
                                6 : dtc=64;
                                7 : dtc=128;
                                8 : dtc=256;
                                9 : dtc=512;
                                10 : dtc=1024;
                                11 : dtc=2048;
                                12 : dtc=4096;
                                13 : dtc=8192;
                                14 : dtc=16384;
                                15 : dtc=32768;
                                default:dtc=65535;
                endcase
                end       
                always @(dec,dtc)
                begin
                if (dec==(dtc)) error = 0;
                                else error = 1;
                end
endmodule

Verilog 3x8 decoder with enable (Behavioral)


Verilog 3x8 decoder with enable (Behavioral)


`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////

module dec3x8enbehav(i,en,dec);
input [2:0]i;
input en;
output [7:0]dec;
reg [7:0]dec;
always @ (i or en)
begin
if (en==0) dec=7'b00000000;
                                else if (en==1)
                                                case (i)
                                                                0 : dec=7'b00000001;
                                                                1 : dec=7'b00000010;
                                                                2 : dec=7'b00000100;
                                                                3 : dec=7'b00001000;
                                                                4 : dec=7'b00010000;
                                                                5 : dec=7'b00100000;
                                                                6 : dec=7'b01000000;
                                                                7 : dec=128;
                                                                default:dec=256;
                                                endcase
                                else dec=256;
end



endmodule





Test

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
module dec3x8enbehavVtf;
                reg [2:0] i;
                reg [2:0] ctr;
                reg en;
                wire [7:0] dec;
                reg [7:0] dtc;
                reg error;
                reg clk;
               
                dec3x8enbehav uut (     .i(ctr),    .en(en),               .dec(dec)             );
                initial begin
                                i = 0;
                                clk=0;
                                ctr=0;
                                en=0;
                #100;
                 end
                always
                begin
                #20 clk = ~clk;
                end
                always
                begin
                #300 en = ~en;
                end       
                always @ (posedge(clk))
                begin
                ctr = ctr+1;
                end       
                always @ (ctr or en)
                begin
                if (en==0) dtc=7'b00000000;
                                else if (en==1)
                case(ctr)
                                0 : dtc=8'b00000001;
                                1 : dtc=8'b00000010;
                                2 : dtc=8'b00000100;
                                3 : dtc=8'b00001000;
                                4 : dtc=8'b00010000;
                                5 : dtc=8'b00100000;
                                6 : dtc=8'b01000000;
                                7 : dtc=8'b10000000;                      
                                default:dtc=8'b11111111;
                endcase
                end
                always @(dec,dtc)
                begin
                if (dec==(dtc)) error = 0;
                                else error = 1;
                end
endmodule

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