Friday, January 3, 2014

RAM Verilog code and Verilog Test fixtures





VERILOG CODE (.v) :

`timescale 1ns / 1ps
module RAM( clk,addr,enable,clear,datain,dataout,read_en, write_en);
parameter a=2;
parameter w=4;

input clk,enable,clear,read_en, write_en;
input [a-1:0]addr;
input [w-1:0]datain;
output [w-1:0]dataout;
reg [w-1:0]dataout;
reg [w-1:0] reg_array [((2**a)-1):0];


integer i;
integer j;


always @(posedge(clk))

                begin    
               
                if(clear==1'b0)
                begin
                for(i=0;i<((2**a));i=i+1) reg_array[i] = 0;
                end
               
                else if(enable==1'b0)
                begin
                for(j=0;j<w;j=j+1) dataout[j] = 1'bZ;
                end
               
               
                else if((read_en==1'b1) && (write_en==1'b0))
                dataout = reg_array[addr];
               
                else if((read_en==1'b0) && (write_en==1'b1))
                reg_array[addr] = datain;
               
                else if (read_en==1'b1 && (write_en==1'b1))
                dataout = 0;
               
                else if (read_en==1'b0 && (write_en==1'b0))
                dataout = 0;
               
                end

endmodule




















 


Verilog Test Fixture 




`timescale 1ns / 1ps


////////////////////////////////////////////////////////////////////////////////
module RAMvtf;

parameter a=2;
parameter w=4;
                // Inputs
                reg clk;
                reg [a-1:0]addr;
                reg enable;
                reg clear;
                reg [w-1:0]datain;
                reg read_en;
                reg write_en;
                reg [3:0] dataout_tc;
                reg error =0;
                reg [w-1:0] reg_array [((2**a)-1):0];
                // Outputs
                wire [3:0] dataout;
integer i;
                // Instantiate the Unit Under Test (UUT)
                RAM uut (
                                .clk(clk),
                                .addr(addr),
                                .enable(enable),
                                .clear(clear),
                                .datain(datain),
                                .dataout(dataout),
                                .read_en(read_en),
                                .write_en(write_en)
                );

                initial begin
                                // Initialize Inputs
                                clk = 0;
                                addr = 03;
                                enable = 1;
                                clear = 0;
                                datain = 2;
                                read_en = 0;
                                write_en = 0;
                                #100;
       
                end

                always
                begin
                #10 clk=~clk;
                end
               

                always
                begin
                #300 datain=datain+1;
                end
               
                always
                begin
                #100 write_en=~write_en;
                end

                always
                begin
                #200 read_en=~read_en;
                end
  
                always
                begin
                #1000 enable=~enable;
                end
               
                always
                begin
                #50 clear=1;
                end
               
                always
                begin
                #250 addr=addr+1;
                end
               
               
always @(posedge(clk))

                begin    
               
                if(clear==1'b0)
                begin
                for(i=0;i<4;i=i+1) reg_array[i] = 0;
                end
               
                else if(enable==1'b0)
                begin
                dataout_tc = 4'bZZZZ;
                end
               
               
                else if((read_en==1'b1) && (write_en==1'b0))
                dataout_tc = reg_array[addr];
               
                else if((read_en==1'b0) && (write_en==1'b1))
                reg_array[addr] = datain;
               
                else if (read_en==1'b1 && (write_en==1'b1))
                dataout_tc = 0;
               
                else if (read_en==1'b0 && (write_en==1'b0))
                dataout_tc = 0;
               
                end
               
                always
                begin
                #1 if(dataout == dataout_tc) error=0;
                else error =1;
                end
endmodule





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