Sunday, July 10, 2011

2x4 decoder VERILOG CODE



This is the VERILOG CODE (.v) For
2 to 4 Decoder


`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module dec2x4en_case1(i,en,dec);
input [1:0]i;
input en;
output [3:0]dec;
reg [3:0]dec;
always @ (i or en)
begin
if (en==0) dec=4'b0000;
else if (en==1)
case (i)
0 : dec=4'b0001;
1 : dec=4'b0010;
2 : dec=4'b0100;
3 : dec=4'b1000;
default:dec=4'b1111;
endcase
else dec=4'b1111;
end
endmodule

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